Title: Efficient low-area, high-frequency hardware implementations of shadow lightweight block ciphers for resource-constrained IoT devices and sensor networks

Authors: G. Krishna Pranav; Zeesha Mishra; Bibhudendra Acharya; Bijayananda Patnaik

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology, Raipur, 492010, India ' Department of Microelectronics and VLSI, UTD, Chhattisgarh Swami Vivekanand Technical University, Chhattisgarh, 491107, India ' Department of Electronics and Communication Engineering, National Institute of Technology, Raipur, 492010, India ' Department of Electronics and Communication Engineering, National Institute of Technology, Raipur, 492010, India

Abstract: The Internet of Things (IoT) is referred to as the next social application era, with its users and applications growing at an exponential rate. As technology advances, modern applications require optimised requirements such as low area, low power, and low cost, among others. Cryptography fails to meet the above-limited resource criteria, paving the way for lightweight cryptography, which deals with modern limited resource issues very efficiently. This paper discusses the lightweight shadow block cipher, which uses a generalised Feistel structure for encryption. A 4-Clock Loop Unrolled architecture (S1) of Shadow-32 and Pipelined architecture of Shadow-64 (S2) are proposed to improve the algorithm's performance, i.e., by increasing throughput and frequency. The performance metrics are compared to various lightweight block ciphers, with the best improvements in throughput of 365.6% and 140% over conventional architectures in S1 and S2, respectively.

Keywords: IoT; Internet of Things; cryptography; shadow; encryption; lightweight cryptography; FPGA; field programmable gate array.

DOI: 10.1504/IJHPSA.2023.139896

International Journal of High Performance Systems Architecture, 2023 Vol.11 No.4, pp.216 - 224

Received: 25 May 2023
Accepted: 11 Dec 2023
Published online: 09 Jul 2024 *

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