Article: Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices Journal: International Journal of Embedded Systems (IJES) 2017 Vol.9 No.4 pp.337 - 352 Abstract: Field programmable gate array (FPGA) technology is being adopted in many digital systems, hence the demand for security increases, especially when intrinsic vulnerabilities of programmable devices jeopardise the intellectual properties (IPs). New high and medium-end FPGA devices have built-in mechanisms that, exploiting encryption primitives, are able to avoid IP piracy by preventing cloning and reverse engineering, but low-end FPGA families still lack security solutions. Recently, in the literature, a great researching effort has been done on physically unclonable functions (PUFs), which are eligible to be a fundamental means for authenticating integrated circuits. They can be adopted to guarantee protection against IP violations by implementing locking finite state machines (FSMs) on any device. In this paper, we show two implementations of the Anderson PUF, a good scalable and high reliable PUF architecture, on the Xilinx Spartan-3E family, which can be adopted to introduce the locking mechanism. In the experimental result, we show the quality parameters for signatures generated from proposed Anderson PUFs and the overhead introduced by the locking mechanism through an FSM. Inderscience Publishers - linking academia, business and industry through research

Title: Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices

Authors: Mario Barbareschi; Pierpaolo Bagnasco

Addresses: Department of Electrical Engineering and Information Technologies, University of Naples Federico II, Naples, NA, Italy ' Department of Electrical Engineering and Information Technologies, University of Naples Federico II, Naples, NA, Italy

Abstract: Field programmable gate array (FPGA) technology is being adopted in many digital systems, hence the demand for security increases, especially when intrinsic vulnerabilities of programmable devices jeopardise the intellectual properties (IPs). New high and medium-end FPGA devices have built-in mechanisms that, exploiting encryption primitives, are able to avoid IP piracy by preventing cloning and reverse engineering, but low-end FPGA families still lack security solutions. Recently, in the literature, a great researching effort has been done on physically unclonable functions (PUFs), which are eligible to be a fundamental means for authenticating integrated circuits. They can be adopted to guarantee protection against IP violations by implementing locking finite state machines (FSMs) on any device. In this paper, we show two implementations of the Anderson PUF, a good scalable and high reliable PUF architecture, on the Xilinx Spartan-3E family, which can be adopted to introduce the locking mechanism. In the experimental result, we show the quality parameters for signatures generated from proposed Anderson PUFs and the overhead introduced by the locking mechanism through an FSM.

Keywords: IP protection; field programmable gate array; FPGA security; physically unclonable functions; PUFs; fuzzy extractor; Anderson PUF; Xilinx Spartan-3E.

DOI: 10.1504/IJES.2017.086135

International Journal of Embedded Systems, 2017 Vol.9 No.4, pp.337 - 352

Received: 09 Dec 2015
Accepted: 24 Jul 2016
Published online: 27 Aug 2017 *

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Title: Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices

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