Title: Improved reconfigurable hyper-pipeline soft-core processor on FPGA for SIMD

Authors: Maheswari Raja; Pattabiraman Venkatasubbu

Addresses: School of Computing Science and Engineering, VIT University, Vandalur-Kelambakkam Road, Chennai-600127, Tamilnadu, India ' School of Computing Science and Engineering, VIT University, Vandalur-Kelambakkam Road, Chennai-600127, Tamilnadu, India

Abstract: Reconfiguration is a powerful computational model in which the processors can be changed dynamically during the execution phase of the system. This paper presents dynamic reconfigurable register file allocation in hyper pipelined OR1200 (Open RISC) for single instruction multiple data (SIMD). The OR1200 instantly reconfigures the actual register file to the reconfigurable register file according to the requirement of the application. The unused general purpose registers obtained during the reconfiguration process can be used for hyper pipelining technique which improves overall performance of the single core processor system. Thus releasing the unused register reduces the power consumption and increases the execution speed of OR1200. This proposed reconfigurable technique is implemented using Verilog and it is tested using MediaBench multimedia benchmark dataset which ensures reduced register utilisation of 16.80% for multimedia dataset and power reduction up to 72.7% with reconfigurable modules. The proposed technique is configured in Virtex-6 field programmable gate array (FPGA) and results are analysed with the existing and proposed reconfigured OR1200.

Keywords: dynamic reconfiguration; MediaBench; soft-core; field programmable gate array; FPGA; hyper pipeline.

DOI: 10.1504/IJHPCN.2017.084249

International Journal of High Performance Computing and Networking, 2017 Vol.10 No.3, pp.207 - 217

Received: 10 Jul 2015
Accepted: 19 Sep 2015
Published online: 22 May 2017 *

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