Title: A high-level exploration tool for three-dimensional network-on-chip

Authors: Ji Wu; Dongqing Xie; Lin Tang

Addresses: School of Computer Science and Educational Software, Guangzhou University, Guangzhou, 510006, China ' School of Computer Science and Educational Software, Guangzhou University, Guangzhou, 510006, China ' School of Computer Science and Educational Software, Guangzhou University, Guangzhou, 510006, China

Abstract: The convergence of 3D technology and NoC, the so-called 3D NoC, that freedom of interconnects in the vertical dimension can create new architectures, and has already proved higher performance than traditional 2D NoCs. In this paper, we explore the architectural design of 3D NoC and introduce a compositive model of fabrication cost, network throughput and power consumption, supporting six 3D NoC architectures, 3D mesh, hyper octagon, ciliated mesh, separate mesh, generic fat tree (SPIN) and butterfly fat tree (BFT), to explore different 3D design options of 3D NoCs. The model allows partition of IPs across different dies in 3D stack. Based on the model an estimation tool, 3D-partition, is created and validated by comparing its results with those obtained from NIRGAM. Effects of various 3D NoC architectures under different 3D IC partition strategies on cost, throughput and power consumption are explored to demonstrate the utility of the tool. It provides economic and performance reference to designing 3D ICs for volume production in the future.

Keywords: 3D NoC; design space exploration; multi-core processor design; microarchitectures; network-on-chip; fabrication cost; network throughput; energy consumption.

DOI: 10.1504/IJCSE.2017.082881

International Journal of Computational Science and Engineering, 2017 Vol.14 No.2, pp.164 - 178

Received: 16 Oct 2014
Accepted: 16 Apr 2015
Published online: 15 Mar 2017 *

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