Title: Investigation of novel symmetric and asymmetric multilevel converter topology with reduced power switches

Authors: Jagabar Sathik Mohd. Ali; Ramani Kannan

Addresses: Department of Electrical Engineering, J.J. College of Engineering and Technology, Trichy 620 008, Tamil Nadu, India ' Department of Electrical Engineering, K.S.Rangasamy College of Technology, Tiruchengode 637 215, Tamil Nadu, India

Abstract: The multilevel inverter has tremendous challenges to improve the power quality in DC/AC high power application. Multilevel inverter is drawing more attention due to modularity and robustness, especially high voltage applications. In conventional multilevel inverters require a more number of switches and complex switching circuits and size is bulky. This paper proposes a novel multilevel power converter topology with reduced power switches and gate driver circuit without affecting state-of-art necessities. This proposed topology has minimum switching and conduction losses, low voltage stress (dv/dt), low electromagnetic interference, low total harmonic distortion (THD) and better efficiency. Both symmetric and asymmetric methods are simulated using MATLAB/SIMULINK tool. Based on simulation, the prototype experimental setup has been made and results are verified.

Keywords: H-bridge inverters; multilevel converters; nearest level control modulation; reduced power switches; gate driver circuits; symmetric methods; asymmetric methods; simulation.

DOI: 10.1504/IJPELEC.2015.075433

International Journal of Power Electronics, 2015 Vol.7 No.3/4, pp.226 - 242

Received: 27 Oct 2014
Accepted: 05 Nov 2015
Published online: 22 Mar 2016 *

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