Title: A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies

Authors: Xiaofang Wang; Sotirios G. Ziavras

Addresses: Department of Electrical and Computer Engineering, Villanova University, Villanova, PA 19085, USA ' Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102, USA

Abstract: Recent advances in field-programmable gate array (FPGA) technologies have made feasible the implementation of low-cost parallel computing platforms for high-performance matrix computations. Compared to conventional multiprocessor systems, the resulting multiprocessors-on-a-programmable-chip (MPoPC) can provide unique advantages and opportunities in both software and hardware. It is shown in this paper that the performance of an MPoPC can be improved dramatically by adapting slightly intellectual property (IP)-based processing elements, and customising the memory and the interconnection network. The parallel LU factorisation of large, sparse doubly-bordered block diagonal (DBBD) matrices is employed as an application example. To enhance further the performance by software techniques, a run-time load balancing strategy for this algorithm is proposed and analysed. Extensive experimental results on benchmark matrices of size up to 7,917 × 7,917 for power networks demonstrate the effectiveness of our effort.

Keywords: field-programmable gate arrays; FPGA; multiprocessors-on-a-programmable-chip; MPoPC reconfigurable systems; parallel LU factorisation; doubly-bordered block diagonal; DBBD; dynamic load balancing; matrix operations; power grid; parallel computing.

DOI: 10.1504/IJCSE.2015.067043

International Journal of Computational Science and Engineering, 2015 Vol.10 No.1/2, pp.181 - 191

Published online: 25 Jan 2015 *

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