Title: FPGA-based parallel architecture for PID control algorithm and HDL co-simulation

Authors: T. Ananthan; M.V. Vaidyan

Addresses: Department of Electrical Engineering, National Institute of Technology Calicut, Kerala-673601, India ' Department of Electrical Engineering, National Institute of Technology Calicut, Kerala-673601, India

Abstract: This paper aims to describe a dedicated high throughput parallel architecture for digital proportional-integral-derivative (PID) controller along with its field programmable gate array (FPGA) and application specific integrated circuit (ASIC) implementations. The processing speed of the controller depends on design of arithmetic units. In this context, this design incorporates parallel multipliers and a parallel adder to enhance the processing speed. This design is deeply pipelined to achieve high throughput. The algorithm is prototyped on Xilinx FPGA and implemented in 180 nm technology using cadence RTL complier. The performance of the controller is analysed by the results from a dc-dc buck converter control system through hardware descriptive language (HDL) co-simulation. Electronic design automation (EDA) simulator link interacts with hardware and software in MATLAB/Simulink environment and in this environment the response of the buck converter control system prior to hardware implementation is shown.

Keywords: field programmable gate arrays; FPGA; ASIC; dc-dc buck converter; parallel architecture; PID control; HDL co-simulation; hardware descriptive language; simulation; controller design.

DOI: 10.1504/IJES.2013.057703

International Journal of Embedded Systems, 2013 Vol.5 No.4, pp.239 - 247

Received: 11 Sep 2012
Accepted: 29 May 2013
Published online: 19 Jul 2014 *

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