Title: An enhanced architecture for pattern matching in FPGA for intrusion detection in wireless sensor networks
Authors: A. Babu Karuppiah; S. Rajaram
Department of ECE, Velammal College of Engineering and Technology, Viraganoor Rameshwaram Road, Viraganoor, Madurai, Tamilnadu – 625009, India
Department of ECE, Thiagarajar College of Engineering, Madurai, Tamilnadu – 625 015, India
Abstract: Due to increasing number of network worms and virus, network users are vulnerable to malicious attacks. A network intrusion detection system (NIDS) provides an effective security solution. It monitors network traffic for suspicious data patterns, and informs system administrators to take proper actions. Implementing NIDS in WSNs have unique constraints as compared to traditional networks making the implementation of existing security measures impracticable due to limitation in data memory, code space and energy to power the sensor. In this paper, a novel FPGA-based signature match co-processor structural design is proposed. The computational complexity of our proposed bitmap encoder based NIDS is compared with ROM based NIDS. Experimental results show that the proposed architecture due to the reduction in the hardware leads to an efficient reduction in the size of the sensor nodes, increases the speed of the network and decreases the power consumption of the WSN.
Keywords: network intrusion detection system; NIDS; FPGA; pattern matching; shift-or algorithm; wireless sensor networks; WSNs; field-programmable gate arrays; network worms; network viruses; malicious attacks; network security; node size; network speed; power consumption; energy consumption; signature match; co-processor structural design; bitmap encoders.
Int. J. of Mobile Network Design and Innovation, 2012 Vol.4, No.3, pp.119 - 129
Available online: 07 Feb 2013