Title: An efficient routing technique for mesh-of-tree-based NoC and its performance comparison

Authors: K. Manna; S. Chattopadhaya; I. Sengupta

Addresses: School of Information Technology, Indian Institute of Technology Kharagpur, Kharagpur 721302, India. ' Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, India. ' Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, India

Abstract: This paper presents a new dimension ordered routing (DOR) algorithm for mesh-of-tree (MoT)-based network-on-chip (NoC) designs. A simple addressing scheme has been used in this new algorithm. The addressing scheme enables us to reduce the minimum flit-size for a 4 × 4 MoT to 16 bits, compared to 32 bits in the previously reported works. The algorithm has been proved to be deadlock, live-lock and starvation free. It also ensures shortest-path routing for the packets. It results in significant saving in the energy consumed by the network. It allows us to vary router complexity flexibly while planning the MoT-based NoC for application specific system-on-chip (SoC) synthesis. Performance and cost metric comparison with other topologies shows the proposed MoT to be better than many of them.

Keywords: mesh-of-tree; MoT; interconnection networks; network-on-chip; NoC design; deterministic routing algorithms; dimension ordered routing algorithms; DOR algorithms; yx-routing algorithms; system-on-chip; SoC synthesis.

DOI: 10.1504/IJHPSA.2012.047568

International Journal of High Performance Systems Architecture, 2012 Vol.4 No.1, pp.25 - 37

Received: 13 Sep 2011
Accepted: 12 Mar 2012
Published online: 02 Sep 2014 *

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