Title: Process costing of the microchip

 

Author: Bhaskaran Gopalakrishnan, Dipesh Gajera, Deepak P. Gupta, Ragu Athinarayanan, Subodh A. Chaudhari

 

Addresses:
Department of IMSE, West Virginia University, P.O. Box 6070, Morgantown, WV 26506, USA.
Department of IMSE, West Virginia University, P.O. Box 6070, Morgantown, WV 26506, USA.
Department of Industrial and Engineering Technology, Southeast Missouri State University, One University Plaza, MS 6825, Cape Girardeau, MO 63701, USA.
Department of Industrial and Engineering Technology, Southeast Missouri State University, One University Plaza, MS 6825, Cape Girardeau, MO 63701, USA.
Department of IMSE, West Virginia University, P.O. Box 6070, Morgantown, WV 26506, USA

 

Journal: Int. J. of Industrial and Systems Engineering, 2011 Vol.8, No.3, pp.326 - 345

 

Abstract: The CMOS microchip is the workhorse of the semiconductor industry. The manufacturing model was formed with practical processing times, number of machines, steps of manufacturing process, labour cost and time required, construction costs, land costs, etc. as input parameters. This cost model attempts to analyse costs and calculate the cost per chip. Different sections of costs have been individually analysed in turn to reflect their impact on the finished product. A simulation model has been run to reflect an actual semiconductor manufacturing scenario. Simulation model is also used to estimate labour time and cost required for the process. The cost was calculated based on yield, number of chips/wafer and total expenditure by the fabrication unit. A simulation model was created in Arena 6.0 professional version, which allows the user to make changes to the model to reflect the changes in the fabrication unit.

 

Keywords: cost estimation; semiconductor manufacturing; simulation; Arena; CMOS microchips; cost modelling; simulation; wafer fabrication; process costing.

 

DOI: http://dx.doi.org/10.1504/IJISE.2011.041541

 

Available online 25 Jul 2011

 

 

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