Title: Real-time reconfigurable cache for low-power embedded systems

Authors: Geng-Cyuan Jheng, Dyi-Rong Duh, Cheng-Nan Lai

Addresses: Department of Computer Science and Information Engineering, National Chi Nan University, Puli, Nantou Hsien 54561, Taiwan. ' Department of Computer Science and Information Engineering, National Chi Nan University, Puli, Nantou Hsien 54561, Taiwan. ' Department of Information Management, National Kaohsiung Marine University, Kaohsiung City 81143, Taiwan

Abstract: Modern embedded systems execute a small set of applications or even a single one repeatedly. Specialising cache configurations to a particular application is well-known to have great benefits on performance and power. However, the fact that the behaviour of an application varies from phase to phase has been shown in recent years. Tuning cache configuration to fit a target application in different phases gives a further improvement in power consumption. This work presents a mechanism which determines the optimal configurations in different phases during an execution process. By applying corresponding cache configuration for each time interval of an execution process on L1 instruction cache, this work shows that on average 91.6% energy saving is obtained by comparing with average energy consumption of all four-way set-associative caches in search space. On average 5.29% power reduction is achieved by comparing with energy consumption of benchmarks with their respective global optimal cache configurations.

Keywords: reconfigurable cache; embedded systems; power consumption; benchmark; real-time systems; cache configurations.

DOI: 10.1504/IJES.2010.039027

International Journal of Embedded Systems, 2010 Vol.4 No.3/4, pp.235 - 247

Published online: 11 Mar 2011 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article