An analytic evaluation on soft error immunity enhancement due to temporal triplication Online publication date: Wed, 24-Jan-2018
by Ryutaro Doi; Masanori Hashimoto; Takao Onoye
International Journal of Embedded Systems (IJES), Vol. 10, No. 1, 2018
Abstract: Chip-level soft error rate is increasing owing to the device miniaturisation and larger-scale integration. Soft errors are one of the major factors that degrade the reliability of integrated circuits, and soft error aware design is demanded for applications that cannot allow any failures. As one of the soft error countermeasures, spatial redundancy has been widely studied and adopted in real products because of its small speed overhead and easiness of implementation. On the other hand, temporal redundancy, which is another well-known technique, is rarely adopted in practical applications and its usefulness is not comparatively evaluated. This paper analytically evaluates the soft error immunity enhancement, thanks to temporal triplication. The evaluation result shows that the failure rate reduction of the temporal triplication is comparable to that of the spatial triplication in the supposed pipeline hardware and computation model.
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Embedded Systems (IJES):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email subs@inderscience.com
Our Blog 
Follow us on Twitter 
Visit us on Facebook