Design space exploration for low-power channel decoder in embedded LDPC-H.264 joint decoding architecture
by Yoon Seok Yang; Gwan Choi
International Journal of Information Technology, Communications and Convergence (IJITCC), Vol. 1, No. 4, 2011

Abstract: This paper presents a low-power design scheme to lower baseband energy consumption using joint source decoding and dynamic voltage and frequency scaling (DVFS). This scheme combines unequal error protection (UEP) developed for error resilient video coding with a variable iteration low density parity check (LDPC) decoder to trade off performance against energy consumption. Using the proposed method, we determine LDPC decoding configurations that achieve minimum energy consumption while satisfying prespecified image quality at the receiver. The implementation results yield 17%, 37%, 52% power reductions with 0, 0.3, 1.1 dB peak signal to noise ratio (PSNR) degradation at 3.6 dB SNR in Foreman test stream respectively.

Online publication date: Sat, 28-Feb-2015

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