Numerical simulation approach on stress and strain for chip scale package under thermal cycling Online publication date: Tue, 09-Jun-2009
by Yang Ping, Wei Li
International Journal of Manufacturing Technology and Management (IJMTM), Vol. 18, No. 3, 2009
Abstract: In this paper, a two dimensional with one-half of cross-section model and a three dimensional with one-fourth of whole package model were built respectively to simulate the thermal stress and strain of CSP-SOC. The simulation results show the maximum deformation of the whole package occurs in PCB and the maximum stress and strain occurs in the outer solder balls. In the mean time, it is found that the maximum elastic strain exists in the interface of the solder balls and PCB, but the minimum strain exists in the underfill tape, the whole package stress occurs in the edge area of chip.
Online publication date: Tue, 09-Jun-2009
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