Field Programmable Gate Array based floating point hardware design of recursive k-means clustering algorithm for Radial Basis Function Neural Network Online publication date: Sun, 25-Jan-2009
by S.P. Joy Vasantha Rani, P. Kanagasabapathy, L. Suganthi
International Journal of Intelligent Systems Technologies and Applications (IJISTA), Vol. 6, No. 1/2, 2009
Abstract: In this paper, the hardware design of Radial Basis Function Neural Network (RBFNN), which is capable of dealing with floating point arithmetic operations and hardware architecture to calculate the centres of hidden layer using the k-means algorithm are proposed. The RBFNN are very much useful in adaptive control applications. Hardware implementation of neural network will give much faster training than traditional processors and also relatively inexpensive. The architecture of RBFNN is based on a computational model whose main features are: the capability to exploit the inherent parallelism of neural networks and to increase or decrease the number of neurons, aiming flexibility of the network. The design has been done with Very High Speed Integrated Circuit Hardware Description Language (VHDL). The results are verified and analysed in the MATLAB environment. In this work, the floating point hardware gives best precision and also very much useful for wide dynamic range requirements. The design was tested and synthesised with the help of Virtex-II pro device. The simulation and synthesis results show the effectiveness and speed of training.
Online publication date: Sun, 25-Jan-2009
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