Title: A novel method for reduction of leakage current in MOSFET

Authors: Debasis Mukherjee; B.V. Ramana Reddy

Addresses: Department of Electronics and Communication Engineering, Sir Padampat Singhania University, Bhatewar, Udaipur 313601, Rajasthan, India; USICT, GGSIPU, Delhi 110078, India ' University School of Information, Communication and Technology, Guru Gobind Singh Indraprastha University, Sector 16C, Dwarka, Delhi 110078, India

Abstract: In this paper, structural modification of conventional bulk MOSFET has been proposed for minimisation of subthreshold leakage current. Key structural features of bulk MOSFET have been kept unaltered. Comparison of conventional and proposed structure has been presented for a 20 nm NMOS with 0.8 volt Vdd. The proposed structure is capable of reducing subthreshold leakage current even at very low drain voltage when the gate voltage is zero. Around 55% reduction of OFF current has been obtained when drain voltage is at Vdd and gate voltage is zero. The methodology proposed does not have any special requirement at the circuit level, and can be combined with all circuit level methodologies. The proposed structure is named as 'defensive MOSFET' as it looks like a defensive shield. Structural dimensions of 20 nm MOSFET generation have been taken from the 2011 edition of International Technology Roadmap for Semiconductors or ITRS. All simulation processes have been executed by Sentaurus G-2012.06 Technology Computer Aided Design or TCAD software.

Keywords: 20 nm; NMOS; leakage; subthreshold; device level; bulk; CMOS; VLSI; defensive MOSFET; ITRS; Sentaurus; TCAD.

DOI: 10.1504/IJCONVC.2018.091115

International Journal of Convergence Computing, 2018 Vol.3 No.1, pp.48 - 61

Received: 03 May 2017
Accepted: 27 Sep 2017
Published online: 10 Apr 2018 *

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