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Title: Design of a parity preserving reversible full adder/subtractor circuit

Authors: Shiva Rahbar Arabani; Mohammad Reza Reshadinezhad; Majid Haghparast

Addresses: Department of Computer Engineering, University of Isfahan, Isfahan, Iran ' Department of Computer Engineering, University of Isfahan, Isfahan, Iran ' Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran

Abstract: The reversible logical circuits, due to their economised power consumption in comparison with their counterparts with binary circuits, have become a major issue of study. A reversible circuit with equal parity of inputs and outputs is considered as a parity preserving circuit. In such circuits, any fault effecting only one logical signal, is detectable at the main outputs. A new 5 × 5 parity preserving reversible block called RRH is proposed which would operate as a half adder/subtractor and a full adder/subtractor. The outcome of comparisons indicates that this proposed block outperforms its counterparts with respect to the number of constant inputs and garbage outputs, quantum cost and circuit dimensions.

Keywords: reversible logic; half adder/subtractor; full adder/subtractor; parity preserving; quantum cost; garbage outputs; constant inputs; circuit dimensions.

DOI: 10.1504/IJCISTUDIES.2018.090164

International Journal of Computational Intelligence Studies, 2018 Vol.7 No.1, pp.19 - 32

Available online: 22 Feb 2018 *

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