Title: Novel concept for reducing the power consumption of look ahead carry adder circuit by using stackiabatic technique
Authors: Kapil Mangla; Anil Kumar
Addresses: Al-falah School of Engineering and Technology Dhauj, Faridabad, Haryana, India ' Al-falah School of Engineering and Technology Dhauj, Faridabad, Haryana, India
Abstract: For many years, designing of the high speed low power circuits with CMOS technology was a difficult challenge for the research community. There are various levels at which design problem related to low power and increased demand can be addressed; these levels are - software level, architecture level, algorithm level, circuit level and process technology level. In this paper, we have designed a four-bit look ahead carry adder using CMOS technology. The objective of this paper is to search for different approaches that will reduce the consumption of power of look ahead carry adder. We have designed look ahead carry adder using stackiabatic technique and compared with conventional, adiabatic and stacking techniques.
Keywords: CMOS circuit; very large-scale integrated circuit; VLSI; combinational circuits; tanner EDA; power.
International Journal of Autonomic Computing, 2017 Vol.2 No.4, pp.323 - 340
Available online: 31 Jan 2018 *Full-text access for editors Access for subscribers Purchase this article Comment on this article