Title: Design and implementation of a reconfigurable finite impulse response filter for adaptive systems
Authors: R. Saranya; C. Pradeep; R. Radhakrishnan
Addresses: Department of Electronics and Communication Engineering, NSS College of Engineering, Palakkad, India ' Department of Electronics and Communication Engineering, Mar Baselios College of Engineering and Technology, Peermade, Idukki, India ' Department of Electronics and Communication Engineering, Sasurie College of Engineering, Vijayamangalam, Thirupur, India
Abstract: In this paper, we present the design and implementation of a reconfigurable finite impulse response (FIR) filter for adaptive systems with online fault detection mechanism. An area efficient data path with online fault detection mechanism depending on nature of operands is used to model the FIR filter and is based on the concept of divide and conquers approach. An online fault detection mechanism is introduced by utilising the feature of duplication with comparison where the same calculation is performed twice and the outputs are compared to identify errors. The design is modelled using Verilog HDL, simulated and synthesised using Xilinx ISE 14.2. The design is also modelled using Leonardo spectrum to show the area efficiency of the proposed data path. The design is evaluated using PlanAhead 14.2 on ML 505 development board with Virtex 5 (XC5VLX110T-1FF1136) FPGA which supports partial reconfiguration.
Keywords: dynamic partial reconfiguration; DPR; field programmable gate arrays; FPGA; FIR filters; data path; online fault detection; PlanAhead; reconfigurable filters; finite impulse response filters; adaptive systems; modelling; simulation.
International Journal of Computational Systems Engineering, 2017 Vol.3 No.1/2, pp.82 - 90
Available online: 20 Mar 2017 *Full-text access for editors Access for subscribers Purchase this article Comment on this article