Title: Adaptive weight-based: an exclusive bypass algorithm for L3 cache in a three level cache hierarchy
Authors: Banchhanidhi Dash; Debabala Swain; Bijay K. Paikaray
Addresses: School of Computer Engineering, KIIT University, Bhubaneswar, India ' School of Computer Engineering, KIIT University, Bhubaneswar, India ' Department of CSE, CUTM, Bhubaneswar, India
Abstract: Cache memory plays a decisive role in recent day processors. Current processors use multi-level cache hierarchy to avoid the capacity misses. Still processors have to pay high cost due to conflict misses. To avoid such misses, several replacement techniques are used in the cache memory. Whereas, in a multi-level cache, where enormous applications are running simultaneously, a bypass replacement technique in the last level cache is found significant from the reduced miss cost, CPU performance point of view. This paper presents a similar solution of bypassing in the L3 cache, called adaptive weight-based (AWB) bypass algorithm which shows better performance assessment compared to LRU with different benchmark traces from SPEC.
Keywords: last level cache; LLC design; AWB bypass algorithm; exclusive LLC; adaptive weight-based; frequency tour; three level cache hierarchy; cache memory; L3 cache.
International Journal of Computational Systems Engineering, 2017 Vol.3 No.1/2, pp.74 - 81
Available online: 20 Mar 2017 *Full-text access for editors Access for subscribers Purchase this article Comment on this article