Authors: Kanchan Shailendra Tiwari; Ashwin G. Kothari
Addresses: MESCOE, E&TC Department, Pune, India ' Electronics and Comm. Department, VNIT, Nagpur, India
Abstract: Rough set theory offers a promising solution for discovering knowledge from vague, incomplete and uncertain data. Literature survey shows tremendous research work in reduct computation using software specially developed for rough set theory. However, it becomes quite slow while dealing with larger datasets. New developments and growth in field programmable gate array offer researchers a novel alternative of using it as a hardware accelerator. The goal of this work is to design a hardware accelerator for rough set algorithms using a field programmable gate array. This paper presents modules based on rough set theory. With the usage of multi ports RAM, pipelining in design and parallelism in algorithm, considerable improvement in frequency of overall system is achieved. The proposed design has been tested on Wisconsin Breast Cancer Database. The proposed hardware accelerator will expedite the decision-making process of pathologists and doctors. The simulation results show that the proposed hardware is significantly faster than algorithms running on a general-purpose processor even though the clock frequency of design implemented on field programmable gate array is about 25 times slower.
Keywords: field programmable gate arrays; FPGA; hardware accelerator; rough sets; discernibility matrix; classification; rules; HDL; data mining; intelligent systems; breast cancer; rough set theory; simulation; healthcare technology.
International Journal of Data Mining, Modelling and Management, 2016 Vol.8 No.3, pp.279 - 301
Received: 29 Apr 2014
Accepted: 05 Apr 2015
Published online: 12 Sep 2016 *