Authors: Dinesh S. Kumar; Linu Rose; Alex James
Addresses: Enview R&D Labs LLP, Jumbo Towers, Pothencode, Thiruvananthapuram, Kerala, India ' Enview R&D Labs LLP, Jumbo Towers, Pothencode, Thiruvananthapuram, Kerala, India ' Electrical and Electronic Engineering Department, School of Engineering, Nazarbayev University, Republic of Kazhakhstan
Abstract: The concept of a pseudo-resistive threshold logic circuit that uses a combination of CMOS inverter and bulk driven MOSFET pseudo-resistive divider circuit for designing a universal NOR gate is presented. Inspired from the neuronal firing mechanisms, the inverter implements the binary threshold decision, while pseudo-resistive circuit provides the summation of normalised weighted inputs. The proposed logic gate when tested using the TSMC 0.18 µm low voltage process show an overall improved performances in terms of area, delay and power in comparison with CMOS and pseudo NMOS logic.
Keywords: threshold logic gates; sensory gates; brain logic; CMOS inverters; resistive MOSFET; neuronal firing mechanisms; universal NOR gates.
International Journal of Machine Intelligence and Sensory Signal Processing, 2014 Vol.1 No.2, pp.192 - 198
Received: 08 Jul 2013
Accepted: 12 Dec 2013
Published online: 03 Nov 2014 *