Title: Amdahl's and Hill-Marty laws revisited for FPGA-based MPSoCs: from theory to practice

Authors: Junneng Zhang; Chao Wang; Xi Li; Xuehai Zhou; Aili Wang; Gangyong Jia; Nadia Nedjah

Addresses: School of Computer Science, University of Science and Technology of China, P.O. Box 4, Hefei, Anhui, 230027, China ' School of Computer Science, University of Science and Technology of China, P.O. Box 4, Hefei, Anhui, 230027, China ' School of Computer Science, University of Science and Technology of China, P.O. Box 4, Hefei, Anhui, 230027, China ' School of Computer Science, University of Science and Technology of China, P.O. Box 4, Hefei, Anhui, 230027, China ' School of Software Engineering, Suzhou Institute for Advanced Study, University of Science and Technology of China, Ren'ai Road 188, Jiangsu, Suzhou, 215123, China ' School of Computer Science, Hangzhou Dianzi University, Biayang 2 Street 1158, Hangzhou, Zhejiang, 310018, China ' Department of Electronics Engineering and Telecommunications, State University of Rio de Janeiro, Brazil

Abstract: In this paper we extend and analyse Amdahl's and Hill-Marty laws to general heterogeneous on-chip cluster era, without the abstract limitation of base core equivalents (BCEs). To understand the relative merits between speedup and the cluster characteristics, including microprocessors amount, accelerators speedup, and task partitioning plans, we also analyse the theoretical results about how the extended Amdahl's Law is applied to leverage load balancing of a heterogeneous on-chip cluster. Simulation results demonstrate that our extended model reinforces state-of-the-art performance evaluation methods for hybrid MPSoC architectures and also provide creditable new insights to heterogeneous research communities, in particular for scalable FPGA based on-chip cluster domains.

Keywords: Amdahl's Law; performance evaluation; on-chip clusters; heterogeneous; load balancing; Hill-Marty; FPGA; MPSoCs; microprocessors; accelerator speedup; task partitioning; simulation; field-programmable gate arrays; multiprocessor SoC; system on chip.

DOI: 10.1504/IJHPSA.2014.061466

International Journal of High Performance Systems Architecture, 2014 Vol.5 No.2, pp.115 - 126

Received: 14 Dec 2013
Accepted: 20 Feb 2014

Published online: 26 May 2014 *

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