Authors: S. Vijayan, S. Paramasivam
Addresses: Department of Electrical and Electronics Engineering, Institute of Road and Transport Technology, Erode, India. ' ESAB Engineering Services Limited, Chennai, India
Abstract: In this paper, an FPGA-based digital speed control scheme is presented to overcome the drawbacks in the previous speed control schemes, proposed for Switched Reluctance Motor (SRM) drives. It is based on discrete control algorithm, and requires simple mathematical models. The real-time experimental results given in this paper show that the closed-loop speed control method proposed could provide accurate speed control upto 6.2 rpm depending on the needed operating speed range, with a step response settling time of 0.25-1.05 s. It can also perform accurately at different operating conditions and over a wide range of speeds. Complete descriptions of the experimental system along with FPGA implementation are presented.
Keywords: SRM; switched reluctance motors; speed control; intelligent control; discrete control; PID control; FPGA; field programmable gate array.
International Journal of Intelligent Systems Technologies and Applications, 2009 Vol.7 No.4, pp.414 - 429
Available online: 03 Sep 2009 *Full-text access for editors Access for subscribers Purchase this article Comment on this article