Title: Efficient hardware implementation of KLEIN cipher with power analysis attack resistance

Authors: R. Parthasarathy; Saravanan Paramasivam

Addresses: Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore, India ' Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore, India

Abstract: Lightweight hardware implementation of block ciphers is critical to ensure the safety of data in resource-constrained environments. In this work, two iterative architectures are designed for Klein-64/80/96 and implemented in both the FPGA devices and the ASIC platform. The first architecture is of 64-bit datapath size, utilised a minimum number of slices in FPGAs, and exhibited very good throughput compared to the existing works in the literature. The second architecture utilised a 32-bit datapath with a minimum number of S-boxes and mixcolumns equation, which resulted in an area of 1,451 GE on the ASIC platform, determined using the Cadence tool and 45 nm technology library gpdk045. A correlation power analysis attack is mounted on the FPGA implementation of KLEIN-64 and successfully extracted the 64-bit key. The threshold implementation is defined as a countermeasure to mitigate the power analysis attack and secure the hardware implementation against the power analysis attack.

Keywords: KLEIN cipher; lightweight cryptography; low cost implementation; power analysis attack; threshold implementation.

DOI: 10.1504/IJAHUC.2026.153340

International Journal of Ad Hoc and Ubiquitous Computing, 2026 Vol.51 No.4, pp.189 - 203

Received: 24 Apr 2024
Accepted: 13 Aug 2025
Published online: 01 May 2026 *

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