Title: A power-awareness routing protocol for sustainable low-power wireless networks: FPGA vs. microcontroller implementation

Authors: Aparna M. Telgote; Sudhakar S. Mande

Addresses: Ramrao Adhik Institute of Technology, Nerul, Navi Mumbai, India ' Don Bosco Institute of Technology, Mumbai, India

Abstract: Wireless networks play a vital role in our daily lives; however, addressing the energy efficiency challenge in low-power wireless networks requires innovative strategies. This research explores deploying a centralised power-aware routing protocol (CPARP) on field programmable gate arrays (FPGAs), presenting a promising alternative to traditional microcontroller-based devices. The CPARP enhances power efficiency by strategically selecting data routing paths based on metrics such as transceiver power, delay, and link quality. Comparative analysis shows that the FPGA-based approach achieves up to 47% power savings, reducing current draw from 80 mA to 20 mA while maintaining network performance metrics like latency and packet delivery success rates. Real-time testing reveals that individual microcontroller-based nodes consume only 101 mW. This study not only demonstrates the practical applications and benefits of CPARP but also advocates for exploring alternative hardware platforms. The insights gained contribute to the advancement of wireless network technologies, promoting sustainability and energy efficiency.

Keywords: field programmable gate array; FPGA; ESP32; Spartan 6; Zigbee S2C; X-CTU.

DOI: 10.1504/IJAHUC.2025.143974

International Journal of Ad Hoc and Ubiquitous Computing, 2025 Vol.48 No.2, pp.75 - 93

Received: 27 Mar 2024
Accepted: 31 May 2024
Published online: 16 Jan 2025 *

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