Title: Modelling and optimisation of high-speed KLEIN architectures on FPGA and ASIC platforms for IoT applications

Authors: Pulkit Singh; Rahul Kumar Chaurasiya; Bibhudendra Acharya

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Raipur, Raipur – 492010, Chhattisgarh, India ' Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology Bhopal, Bhopal – 462003, Madhya Pradesh, India ' Department of Electronics amd Communication Engineering, National Institute of Technology Raipur, Raipur – 492010, Chhattisgarh, India

Abstract: Security and privacy are serious issues in the internet of things (IoT) emerging areas. The lightweight cryptographic algorithms are immensely important for secure communication in high-speed IoT applications. The objective of this work is to obtain optimised architectures from scalar and pipelined designs from modified KLEIN cipher implemented on field programmable gate arrays (FPGA) and application specific integrated circuits (ASIC) platforms. This analysis is carried out based on examined hardware metrics such as frequency, area, power, and energy consumption. A one-round scalar implementation shows 73.1% and 93.3% lesser power and 70.7% and 93.1% energy efficient compared to one-round pipelined implementation on both platforms. In addition, this paper demonstrates that modelled and optimised implementations of modified KLEIN cipher show good accuracy compared to state-of-the-art design models. Hence, this paper gives general guidelines for all lightweight block ciphers by noticing the behaviour of modified KLEIN cipher.

Keywords: security; S-box; lightweight cryptography; block cipher; KLEIN.

DOI: 10.1504/IJAHUC.2023.130459

International Journal of Ad Hoc and Ubiquitous Computing, 2023 Vol.42 No.4, pp.207 - 225

Received: 03 Mar 2022
Received in revised form: 21 Apr 2022
Accepted: 16 May 2022
Published online: 21 Apr 2023 *

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