Title: Design of BTI sensor-based improved SRAM for mobile computing applications

Authors: Kumar Neeraj; Jitendra Kumar Das; Hari Shanker Srivastava

Addresses: School of Electronics, KIIT University, Bhubaneshwar, India ' School of Electronics, KIIT University, Bhubaneshwar, India ' ECE Department, Anurag Group of Institutions, India

Abstract: Reliability of electronic components is the major concern as the CMOS technology is scaled down especially in mobile computing applications of MPEG video processor design. Scaling CMOS technology leads to increase in power density per unit area in an exponentially manner. BTI is one of the serious problems in SRAM cell design at low technology level. In this paper, a detection technique is proposed which detects the BTI effect on SRAM using SNM calculation. The proposed prototype is used to detect faults during read and write cycle of aged SRAM, which affects the reliability of the circuit. The diagnostics of fault is done by detection of BTI effect on SRAM using static noise margin (SNM) calculation. The circuit design on CMOS technology is carried out using HSPICE simulator in cadence.

Keywords: static RAM cell; CMOS technology; bias temperature instability; BTI; technology scaling; static noise margin; SNM.

DOI: 10.1504/IJISTA.2020.110008

International Journal of Intelligent Systems Technologies and Applications, 2020 Vol.19 No.4, pp.332 - 347

Received: 08 Dec 2018
Accepted: 03 Apr 2019
Published online: 01 Oct 2020 *

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