The full text of this article/chapter:
A low power scheduling tool for soc designs
by A. Mahdoum, N. Badache, H. Bessalah
12th International Workshop on Systems, Signals and Image Processing (IWSSIP), Vol. 1, No. 1, 2005
Abstract: As semiconductor technology scales down, integration on a chip becomes higher and concerns complex algorithm implementation. Those algorithms concern a variety of applications in many fields. So, adequate scheduling techniques that cope with such a variety of applications are required. The method presented in this paper addresses that request and takes the advantages of both the data flow (ie intensive data flow circuits such as DSPs) and the control flow approaches. Knowing that such a Controlled Data Flow Graph (CDFG) scheduling is not polynomial, an efficient heuristic-based approach is then needed. Thus, subject to user constraints such as time and resources, our heuristic method targets a minimal cycle number while detecting exclusive operations that could be scheduled in the same control step and share the same resource. More, because the power dissipation is a crucial problem for SOC designs, our tool helps the user introduce additional constraints so that the switching power dissipation at a high design level is reduced.
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