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Title: |
An IPv6 enabled packet engine design for home/SOHO routers |
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Author: |
Mingshou Liu, Cheng-Hsien Hsu, Shi-Hong Kuo, Hsang-Chi Tsai 
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Address: |
Department of Electrical Engineering, National Chung Hsing University, Taiwan. ' Department of Electronic Engineering, National Chinyi Institute of Technology, Taiwan. ' Department of Electrical Engineering, National Chung Hsing University, Taiwan. ' Department of Electrical Engineering, National Chung Hsing University, Taiwan |
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Journal: |
International Journal of Internet Protocol Technology 2005 - Vol. 1, No.2 pp. 68 - 74 |
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Abstract: |
Due to the diversity of internet applications and services, traditional software-based networking devices may not be sufficient to afford the processing load imposed by the services. One example is the mixed-version IP environment in which routers must handle the IPv4/IPv6 translation while keeping the IP processing at the line speed. In this paper, we present our work for the design of a protocol optimised packet processing engine that provides common IP services and mixed-version translations. This silicon is written in VHDL and is tested in a Xilinx Vertex II FPGA development board. |
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Keywords: |
system-on-chip; IPv6; packet engine; embedded systems; NAT-PT; routers. |
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DOI: |
10.1504/IJIPT.2005.008041 |
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