Two-steps into energy consumption optimisation due to the mapping of multimedia application to network on chip architecture Online publication date: Wed, 02-Nov-2016
by Djalila Belkebir; Fateh Boutekkouk
International Journal of Intelligent Systems Technologies and Applications (IJISTA), Vol. 15, No. 4, 2016
Abstract: Energy-efficiency is becoming one of the most critical issues in embedded system design that target the multimedia application caused by the increasing number of intellectual property (IP) cores in network on chip (NoC). This paper addresses the optimisation of NoC performances in term of power and latency, we proposed an optimisation technique that is an hybrid based-scheduling algorithm that evolve the cellular automata (CA) with genetic algorithm to solve mapping and scheduling problems where we mixed between GA easiest implementation and achievability of near global optimum solutions with CA simplicity and rigorous mathematical model to achieve our goal. In our algorithm, each transition rule represents a chromosome allowing an automatically programming of the transition rules of the evolutionary cellular automata. Also we have presented new dynamic voltage and frequency scaling technique that automatically detect the voltage change point in order to save power while respecting the timing constraints of the soft real-time multimedia application.
Online publication date: Wed, 02-Nov-2016
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Intelligent Systems Technologies and Applications (IJISTA):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email firstname.lastname@example.org