High-performance ternary logic gates for nanoelectronics Online publication date: Wed, 04-Nov-2015
by Mohammad Hossein Moaiyeri; Mohsen Shamohammadi; Fazel Sharifi; Keivan Navi
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 5, No. 4, 2015
Abstract: This paper presents high-performance ternary buffer (STB), minimum (STMin) and maximum (STMax) circuits using carbon nanotube field effect transistors (CNTFETs). Multiple valued logic (MVL) has been introduced to overcome the complexity and interconnection problems of the binary integrated circuits. In addition, outstanding properties of CNTFETs such as possibility of adopting the desired threshold voltage make them very appropriate for voltage mode MVL circuits design. All circuits are examined in different conditions using Synopsys HSPICE simulator at 32 nm feature size. Power-delay product (PDP) of the proposed designs are lower than the latest presented ternary circuits about 33%, 33% and 64%, respectively.
Online publication date: Wed, 04-Nov-2015
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