A functional unit network for rapid, low-power loop execution
by Georgios Dimitriou; Athanasios Tziouvaras
International Journal of Innovation and Regional Development (IJIRD), Vol. 6, No. 3, 2015

Abstract: Computer architects have focused on advanced processor designs that achieve high performance through multiple cores and multiple threads, and at the same time keep power dissipation low. In this work, we propose a processor back end, specifically designed for rapid loop execution and low power dissipation. This back end consists of a network of functional unit nodes, in which instructions of the loop body are issued only once until loop completion. In this way, we exploit both instruction-level and data-flow parallelism. We attempt to decrease power consumption by turning off the front end and all unused functional units. Simulation results show that the proposed back end can accelerate Livermore loops by up to N/k, for a network of N units and loop body size of N instructions, and an issue rate of k instructions per cycle, when compared to scalar or superscalar RISC execution.

Online publication date: Wed, 12-Aug-2015

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Innovation and Regional Development (IJIRD):
Login with your Inderscience username and password:

    Username:        Password:         

Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com