Acyclic LBDRe: fault-tolerant routing algorithm for network on chip Online publication date: Sat, 19-Jul-2014
by Amit Zinzuwadiya; Renu Verma
International Journal of Embedded Systems (IJES), Vol. 5, No. 1/2, 2013
Abstract: In this paper, as technology scales higher, reliability of network on chip (NoC) becomes key issue. It decreases the transistor reliability by connecting the increasing number of on-chip resources. Consequently, this paper presents an efficient fault tolerant routing algorithm for the NoC architecture. We propose acyclic LBDRe which is based on extended logic-based distributed routing (LBDRe) array. Minimal set of turns are prohibited to avoid deadlock. The algorithm guarantees that not more than 1/3 of all turns in the NoC architecture become prohibited. The proposed routing algorithm outperforms substantially the existing fault tolerant routing algorithms. Simulation results show that the proposed method can noticeably reduce the overall average latency and total network power with minimum hardware cost for the fault tolerant routing algorithm for NoC.
Online publication date: Sat, 19-Jul-2014
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Embedded Systems (IJES):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email email@example.com