A minimalist cache coherent MPSoC designed for FPGAs Online publication date: Sat, 21-Mar-2015
by Jorge Tortato Junior, Roberto A. Hexsel
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 3, No. 2/3, 2011
Abstract: We describe the design and VHDL implementation of a cache coherent MPSoC named minimalist cache coherent MPSoC (MCCM). The system comprises one to eight MIPS-I processors, coherent primary data caches, memory management units, memory controller and the interconnection. We present a detailed account of the implementation, focusing on the shared memory subsystem. A simple benchmark is used to assess the overall system functionality. We compared the size of our design to that of a LEON3-based multiprocessor and found that a four-core LEON3 system needs roughly the same amount of logic/state as a six to eight cores MCCM.
Online publication date: Sat, 21-Mar-2015
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of High Performance Systems Architecture (IJHPSA):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email email@example.com