A minimalist cache coherent MPSoC designed for FPGAs
by Jorge Tortato Junior, Roberto A. Hexsel
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 3, No. 2/3, 2011

Abstract: We describe the design and VHDL implementation of a cache coherent MPSoC named minimalist cache coherent MPSoC (MCCM). The system comprises one to eight MIPS-I processors, coherent primary data caches, memory management units, memory controller and the interconnection. We present a detailed account of the implementation, focusing on the shared memory subsystem. A simple benchmark is used to assess the overall system functionality. We compared the size of our design to that of a LEON3-based multiprocessor and found that a four-core LEON3 system needs roughly the same amount of logic/state as a six to eight cores MCCM.

Online publication date: Sat, 21-Mar-2015

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