Partial SOI superjunction power LDMOS for power IC applications
by Yu Chen, Yung C. Liang, Ganesh S. Samudra, Kavitha D. Buddharaju, Hanhua Feng
International Journal of Power Electronics (IJPELEC), Vol. 2, No. 4, 2010

Abstract: An enabling superjunction device technology, which is fully integrated on the partial silicon on insulator (PSOI) platform using the bulk silicon substrate, is proposed and fabricated. The proposed technology has the potential to eliminate the substrate assisted depletion. It enables the implementation of lateral superjunction power MOSFET (SJ LDMOS) on bulk silicon substrate without sacrificing its thermal performance. In this paper, the approach was demonstrated successfully on both p-i-n diode and planar gate SJ LDMOS devices. The proposed technology has enabled the fabrication of SJ power integrated circuits (PIC) on the bulk silicon substrate for future automotive power electronics applications.

Online publication date: Thu, 07-Oct-2010

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Power Electronics (IJPELEC):
Login with your Inderscience username and password:

    Username:        Password:         

Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email