A hardware mechanism to reduce the energy consumption of the register file of in-order architectures Online publication date: Sat, 03-Jan-2009
by Jose L. Ayala, Marisa Lopez-Vallejo, Carlos A. Lopez-Barrio, Alexander Veidenbaum
International Journal of Embedded Systems (IJES), Vol. 3, No. 4, 2008
Abstract: This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.
Online publication date: Sat, 03-Jan-2009
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