Power-efficient VLIW design using clustering and widening
by Miquel Pericas, Eduard Ayguade, Javier Zalamea, Josep Llosa, Mateo Valero
International Journal of Embedded Systems (IJES), Vol. 3, No. 3, 2008

Abstract: Media applications exhibit large quantities of Instruction-Level Parallelism (ILP), particularly inside of loops. However, exploited ILP is limited by available resources and loop recurrences. To overcome this, current designs replicate memory ports and functional units. But as the number of units grows, the efficiency also reduces dramatically. Clustering and widening are two techniques for enabling wide issue-cores to meet technology constraints in terms of cycle time, area and power. In this paper we evaluate several VLIW designs that use these techniques. From the study we conclude that either clustering, widening or both can yield power-efficient configurations with little area requirements.

Online publication date: Sun, 14-Sep-2008

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