Title: Design of low power VCO based on single ended delay cells

Authors: Dileep Dwivedi; Manoj Kumar

Addresses: University School of Information, Communication and Technology, Guru Gobind Singh Indraprastha University, New Delhi, India ' University School of Information, Communication and Technology, Guru Gobind Singh Indraprastha University, New Delhi, India

Abstract: This paper reports a hybrid ring VCO with low power consumption using single ended delay cells. A 3-stages VCO shows frequency variation from 2.049 GHz to 8.971 GHz with power consumption variation from 0.51 mW to 3.12 mW. In the 5-stages, VCO frequency varies from 1.153 GHz to 5.130 GHz with power consumption from 0.093 mW to 5.581 mW. Further, a 7-stages VCO provides frequency from 0.874 GHz to 3.678 GHz with power consumption from 0.138 mW to 8.041 mW. Tuning range of 125.63%, 126.59% and 123.19% has been achieved with the 3-stages, 5-stages and 7-stages VCO, respectively. Supply voltage has been varied from 1V to 3V. Phase noise of −83.1dBc/Hz at 1MHz, −90.6dBc/Hz at 1MHz and −90.8dBc/Hz at 1MHz have been reported for 3, 5 and 7-stages VCO, respectively. The figure of merit (FoM) of 156.4dBc/Hz, 160.8dBc/Hz and 156.5dBc/Hz has been observed for 3, 5 and 7-stages VCOs, respectively.

Keywords: CMOS; inverter; low power; phase noise; power consumption; voltage controlled oscillator; VCO.

DOI: 10.1504/IJCAD.2016.089647

International Journal of Circuits and Architecture Design, 2016 Vol.2 No.3/4, pp.233 - 245

Received: 03 Mar 2017
Accepted: 03 Aug 2017
Published online: 05 Feb 2018 *

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