Title: Design of 3rd order cascaded multi-bit sigma delta modulator for ADC using internal feedback

Authors: Ms Sonika; D.D. Neema; R.N. Patel

Addresses: Electronics and Communication Department, CSIT, Durg, Chhattisgarh, India; Electrical and Electronics Department, CIT, Rajnanadgaon, Chhattisgarh, India; Electrical and Electronics Department, SSGI, SSTC, Bhilai, Chhattisgarh, India ' Electronics and Communication Department, CSIT, Durg, Chhattisgarh, India; Electrical and Electronics Department, CIT, Rajnanadgaon, Chhattisgarh, India; Electrical and Electronics Department, SSGI, SSTC, Bhilai, Chhattisgarh, India ' Electronics and Communication Department, CSIT, Durg, Chhattisgarh, India; Electrical and Electronics Department, CIT, Rajnanadgaon, Chhattisgarh, India; Electrical and Electronics Department, SSGI, SSTC, Bhilai, Chhattisgarh, India

Abstract: This paper presents a new design of third order cascaded multi-bit sigma delta modulator for analogue to digital converter. The proposed modulator is based on the conventional multibit cascaded sigma delta modulator with interstage feedback topology. Sigma delta systems favours a cascaded multi-bit architecture for higher resolution and wider bandwidth with extra effort focusing on suppressing the analogue nonlinearity. One of the major analogue non-idealities in a multi-bit cascaded sigma delta modulator is the DAC nonlinearity errors and one of the drawbacks is that performance will be limited by un-cancelled noise introducing from the nonlinear errors of multi-bit DAC. The idea of proposed architecture is to create extra feedback paths around the modulator to reduce the DAC error. In this paper, an improved version of cascaded multi-bit sigma delta modulator is proposed to overcome these problems. In addition, a third order cascaded low distortion ADC architecture is also proposed. Simulation results verify the superiority of both the proposed modulators.

Keywords: analogue to digital converter; ADC; sigma delta modulator; noise shaping; MASH; signal to noise plus distortion ratio; signal to noise ratio; SNR; oversampling ratio; modulator design; internal feedback; simulation.

DOI: 10.1504/IJMNDI.2017.082803

International Journal of Mobile Network Design and Innovation, 2017 Vol.7 No.1, pp.37 - 45

Received: 03 Feb 2016
Accepted: 20 May 2016
Published online: 12 Mar 2017 *

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