Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation
by Michael Hubner, Michael Ullmann, Jurgen Becker
International Journal of Embedded Systems (IJES), Vol. 1, No. 3/4, 2005

Abstract: Xilinx Virtex FPGAs have the possibility of dynamical partial runtime reconfiguration. If a system uses this feature with many different configuration bitstreams for substitution of parts in reconfiguration memory, the amount of neccesary memory increases. The sum of memory amounts which have to be provided for the configuration data is not negligible. This fact suggests the investigation of compressing data before they are stored in memory modules of a system. The compressed bitstream data has to be decrompressed before transferring it to the FPGA. This paper shows an approach to compressing configuration data at design time and decompressing them with a hardware module implemented on FPGA while on runtime.

Online publication date: Mon, 05-Jun-2006

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