Integrated modelling and generation of a reconfigurable network-on-chip
by Doris Ching, Patrick Schaumont, Ingrid Verbauwhede
International Journal of Embedded Systems (IJES), Vol. 1, No. 3/4, 2005

Abstract: While a communication network is a critical component for an efficient system-on-chip multiprocessor, there are few approaches available to help with system-level architectural exploration of such a specialised interconnection network. This paper presents an integrated modelling, simulation and implementation tool. The network architecture can be co-simulated with embedded-software to obtain cycle-accurate performance metrics. This allows an energy and performance tuning of the NOC. Next it can be converted into VHDL for implementation. We discuss our approach by designing a flexible network-on-chip and present implementation results. The performance of our automatically generated network is comparable with a reference design directly developed in HDL.

Online publication date: Mon, 05-Jun-2006

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