High performance PLL for multiband GSM applications Online publication date: Mon, 13-Aug-2018
by Umakanta Nanda; Debiprasad Priyabrata Acharya; Debasish Nayak; Prakash Kumar Rout
International Journal of Nanoparticles (IJNP), Vol. 10, No. 3, 2018
Abstract: Dead zone very often poses to be a limitation in the high performance phase locked loops (PLLs). The design of a dead zone free PLL with fast locking and low phase noise capability is proposed. This is achieved by using a voltage variable delay element (VVDE) in the feedback path or reset path of the phase frequency detector (PFD). A feedback from one of the inputs of charge pump circuit is used to retain the overall PFD delay slightly positive to escape dead zone at lesser phase noise. The PLL performance with this proposed PFD is analysed in the cadence design environment. It attains phase noise of −110.5 dBc/Hz at 1 MHz offset frequency which is superior as compared to the other two reported techniques. Achieving this superior phase noise performance the PLL consumes lesser power of 2.56 mW at the cost of 5% extra physical area. This performance is also compared with that of PLL where no delay and fixed delay element is used to reduce the dead zone.
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