A system-level framework for designing and evaluating protocol processor architectures
by Seppo Virtanen, Tero Nurmi, Jani Paakkulainen, Johan Lilius
International Journal of Embedded Systems (IJES), Vol. 1, No. 1/2, 2005

Abstract: To meet the tightening requirements on network hardware, the design of programmable processors with network-optimised hardware, that is, network or protocol processors, has attracted interest. In this paper, we address evaluation of different architectural configurations for such processors, and reuse of previously designed components in later design projects. The proposed system-level framework enables easy and fast experimentation with different protocol processor hardware architecture configurations to estimate their performance characteristics at early stages in the design process. We conclude the paper with examples of designing processors using the framework.

Online publication date: Thu, 26-Jan-2006

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