Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip
by Yunsi Fei, Niraj K. Jha
International Journal of Embedded Systems (IJES), Vol. 1, No. 1/2, 2005

Abstract: We present a functional partitioning method for low power real-time embedded systems. The goal is to partition the system-level specification of a set of task graphs to realise a distributed system whose constituent nodes are systems-on-a-chip (SOCs). The proposed technique merges partitioning and system synthesis into one integrated process, implemented within a genetic algorithm. This technique satisfies both the hard real-time constraints and each SOC area constraint, and performs multi-objective optimisation, with multiple distributed system architectures produced that trade off overall system price and power consumption. Experimental results show the efficacy of the technique.

Online publication date: Thu, 26-Jan-2006

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