GF(2^m) versatile multiplier/adder architecture for cryptographic applications
by Haichour Amina Selma; Hamadouche M'hamed
International Journal of Circuits and Architecture Design (IJCAD), Vol. 2, No. 2, 2016

Abstract: This paper describes a versatile module architecture for performing multiplication and addition in binary finite fields GF(2^m), with applications to cryptography, using a polynomial basis representation. The proposed architecture provides an execution of the most significant bit (MSB)-first bit-serial multiplication for different operand lengths. This arithmetic module has cryptographic relevance, indeed the latter offers architecture with the features of high order of flexibility which allows an easy configuration for different field sizes, and low hardware complexity which results in small area. The evaluation of efficiency of the proposed architecture is based on criteria of time (latency, critical path) and space (gate-latch number).

Online publication date: Wed, 08-Feb-2017

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

 
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Circuits and Architecture Design (IJCAD):
Login with your Inderscience username and password:

Username:        Password:          Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com