Design of quantum cost efficient reversible multiplier using Reed-Muller expressions
by N. Rajeev Pankaj; P. Venugopal; Prasanthi Mortha
International Journal of Computing Science and Mathematics (IJCSM), Vol. 7, No. 3, 2016

Abstract: Reversible logic design is one of the emerging trends in recent years as it is good for low power design. A good number of design methods for reversible multipliers were proposed earlier. In this paper, two bit reversible multiplier was designed using Reed-Muller expressions, and this new reversible multiplier was used to design 4-bit reversible multiplier. The results save 16.9% of quantum cost (QC), 38.5% of garbage outputs (GOs) and 10.7% of constant inputs (CIs) compared to earlier designs. The simulations are done on Xilinx 10.1 and are presented. The methodology is extended for the design of 8-bit and 16-bit multipliers and the reversible logic metrics were presented for different bit lengths.

Online publication date: Sun, 17-Jul-2016

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