Increased digitalisation of flash ADC in modern CMOS process: a review
by Prachi Palsodkar; Pravin Dakhole
International Journal of Circuits and Architecture Design (IJCAD), Vol. 1, No. 4, 2015

Abstract: Recent trends of flash ADC design demands low voltage, low power and high speed operation at low cost, which can achieve through system level, architecture and technology level changes. Traditional flash ADC with analogue comparators and passive elements, face high level of difficulty to meet this requirement. To overcome these sub-micron ADC design issues, a comparator and calibration unit digitalisation approach is adapted and implemented from last decade. In this paper, a brief survey is done on digitalised approach for modern day ADC designs. Threshold quantised comparators for 4 bit flash ADC designed and discussed here along with there performance parameters.

Online publication date: Thu, 22-Oct-2015

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