Characteristic analysis of a novel low power 10T SRAM cell during read and write operations Online publication date: Thu, 22-Oct-2015
by Prashant Upadhyay; Rajib Kar; Durbadal Mandal; Sakti Prasad Ghoshal
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 7, No. 4, 2015
Abstract: This paper focuses on characteristic analysis of a novel 10T SRAM cell. In the proposed cell two voltage sources VS1 and VS2 are used, one of which connected with the bit line and the other connected with the bitbar line, respectively, for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors ST1 and ST2 are also connected in the pull-down paths. Due to the stack effect in the pull-down transistors in OFF condition sub-threshold leakage current is reduced and this causes reduction of static power dissipation. Simulation has been done in 45nm CMOS technology with 0.7 volt power supply with the help of Microwind 3.1 software. The simulation results of power dissipation, noise margin, power delay product and current leakage during read/write operation have been determined and compared to those of other existing SRAM cells.
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