Layout-oriented look up table-based dual threshold approach to reduce leakage
by Sambhu Nath Pradhan; Angshuman Chakraborty; Abhishek Nag; Debanjali Nath
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 7, No. 4, 2015

Abstract: As VLSI process technology is advancing with time, the complexity of the circuitry in a single chip is also increasing. Leakage power has now become a major factor in the power equations of a circuit. This paper deals with the reduction of standby leakage power in a technology specific manner. The proposed approach is based on the parameters obtained in post layout condition, which yields more practical results compared to pre layout analysis. Techniques that are used to reduce the leakage power are input vector control, cell replacement, cell upsizing. Capacitance, delay and leakage values of individual gates are calculated by post layout simulation at 45 nm TSMC technology in CADENCE layout tool.

Online publication date: Thu, 22-Oct-2015

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